library verilog;
use verilog.vl_types.all;
entity REG_374 is
    port(
        clk             : in     vl_logic;
        input_data      : in     vl_logic_vector(7 downto 0);
        output_data     : out    vl_logic_vector(7 downto 0)
    );
end REG_374;
